As computers and electrical appliances are gradually miniaturized, the performance characteristics of semiconductor devices, such as operational speed or noise margin, become very important considerations in achieving continued miniaturization. Accordingly, embedded memory logic devices have been developed in which functions of a logic device and a memory device are combined. The embedded memory logic device may be composed of a cell array region in which a multitude of memory cells are positioned and a logic circuit region which operates on the information stored in the cell array region. In order to improve the operational speed of embedded memory logic devices, self-aligned silicide (salicide) processing technology has been developed for selectively forming a metal silicide film having low resistivity on a gate electrode and source/drain region of a transistor. Complementary MOS (CMOS) circuits are also widely used for improving power consumption characteristics of a semiconductor device. In this case, when the gate electrodes of the NMOS transistor and PMOS transistor are both doped with N-type impurities, a buried channel is formed in the channel region of the PMOS transistor whereas a surface channel is formed in the channel region of the NMOS transistor. The PMOS transistor in which the buried channel is formed may exhibit severe short-channel characteristics which make it difficult to reduce the channel length as compared with the NMOS transistor. Accordingly, methods have been proposed for improving the short-channel characteristics of PMOS transistors as well as NMOS transistors by doping N-type and P-type impurities into the gate electrodes of the NMOS transistor and PMOS transistor, respectively.
FIGS. 1 through 3 are sectional views for explaining a conventional method for fabricating transistors of an embedded memory logic device, in which reference characters "a" and "b" denote a cell array region and a logic circuit region, respectively.
FIG. 1 is a sectional view illustrating a step of forming a gate oxide film 9 and a conductive film 11. First, a P-well region and an N-well region 7 are formed over the main surface of a semiconductor substrate 1 using a conventional twin well forming process. Here, the P-well region is divided into a first P-well region 5a and a second P-well region 5b. The first P-well region 5a is formed in a cell array region (a) in which memory cells are formed, and the second P-well region 5b and the N-well region 7 are formed in a logic circuit region (b). Next, an isolation film 3 defining an active region and a field region is formed in a predetermined area of the resultant structure, and a gate oxide film 9 is formed on the active region. Subsequently, an undoped polysilicon film 11 is formed over the entire surface of the resultant structure having the gate oxide film 9 formed therein.
FIG. 2 is a sectional view illustrating a step of forming first, second and third gate patterns 11a, 11b and 11c, a source/drain region of a cell transistor, and source/drain regions of an NMOS transistor and a PMOS transistor of the logic circuit region. In detail, the undoped polysilicon film 11 is patterned to form a first gate pattern 11a on a predetermined area of the gate oxide film 9 formed on the first P-well region 5a. At the same time, second and third gate patterns 11b and 11b are formed on predetermined areas of the gate oxide film 9 formed on the second P-well region 5b and the N-well region 7, respectively. Then, the first and second gate patterns 11a and 11b and the isolation film 3 are used as ion implantation masks and N-type impurities are selectively ion-implanted into the first and second P-well regions 5a and 5b. The implanted N-type impurities are then thermally treated to form a first low-concentration source/drain region 13a and a second low-concentration source/drain region 13b on the surface of the active region in both sides of the first and second gate patterns 11a and 11b, respectively. Here, the first and second low-concentration regions 13a and 13b have doping concentrations in a range from between about 1.0.times.10.sup.17 /cm.sup.3 to 1.0.times.10.sup.18 /cm.sup.3. Next, the third gate pattern 11c and the isolation film 3 are used as ion implantation masks and P-type impurities are selectively ion-implanted into the N-well region 7. A thermal treatment step may also be performed at a predetermined temperature to form a third low-concentration source/drain region 15 on the surface of the active region adjacent both sides of the third gate pattern 11c. Here, the P-type doping concentration in the third low-concentration region may range from about 1.0.times.10.sup.17 /cm.sup.3 to 1.0.times.10.sup.18 /cm.sup.3.
Now, a CVD oxide film is formed over the entire surface of the resultant structure and is anisotropically etched to form spacers 16 at the sidewalls of the first through third gate patterns 11a, 11b and 11c. Next, the spacers 16, the first and second gate patterns 11a and 11b, and the isolation film 3 are used as ion implantation masks and N-type impurities (e.g., arsenic ions) are selectively ion-implanted into the first and second P-well regions 5a and 5b. A thermal treatment step is then performed at a predetermined temperature to form first and second relatively high-concentration source/drain regions 17a and 17b in the first and second low-concentration source/drain regions 13a and 13b. Here, the first and second high-concentration source/drain regions 17a and 17b have a doping concentration in a range from about 1.0.times.10.sup.19 to 1.0.times.10.sup.21 /cm.sup.3. In this case, in order to dope the first and second high-concentration source/drain regions 17a and 17b at a concentration exceeding 1.0.times.10.sup.19 /cm.sup.3, as described above, the arsenic ions typically must be ion-implanted at a high dose of about 1.0.times.10.sup.15 -5.0.times.10.sup.15 ions/cm.sup.2. However, if the arsenic ions are ion-implanted at a high dose level, ion implantation damage may be generated in the first and second high-concentration source/drain regions 17a and 17b. This implant damage may take the form of crystalline defects such as dislocation defects. Unfortunately, such crystalline defects may not be completely eliminated by subsequent thermal treatment steps. Therefore, junction leakage current may increase between the first and second high-concentration source/drain regions 17a and 17b, and the first and second P-well regions 5a and 5b.
After forming the first and second high-concentration source/drain regions 17a and 17b, as shown, the first and second low-concentration source/drain regions 13a and 13b remain under the spacers 16 formed at the sidewalls of the first and second gate patterns 11a and 11b. As will be understood by those skilled in the art, the remaining first low-concentration source/drain region 13a and the first high-concentration source/drain region 17a in contact therewith constitute a lightly doped drain (LDD) type source/drain region of the cell transistor in the cell array region (a). Also, the remaining second low-concentration source/drain region 13b and the second high-concentration source/drain region 17b in contact therewith constitute a lightly doped drain (LDD) type source/drain region of the NMOS transistor in the logic circuit region (b).
Subsequently, the spacers 16, the third gate pattern 11c and the isolation film 3 are used as ion implantation masks and P-type impurities are selectively ion-implanted into the N-well region 7. These P-type impurities are then thermally treated to cause the formation of third P-type high-concentration source/drain regions 19 (doped to a concentration of 1.0.times.10.sup.19 .about.1.0.times.10.sup.21 /cm.sup.3) in the third low-concentration source/drain region 15. After forming the third high-concentration source/drain regions 19, as shown, the third low-concentration source/drain regions 15 remain under the spacers 16 formed at the sidewalls of the third gate pattern 11c. Here, the remaining third low-concentration source/drain region 15 and the third high-concentration source/drain region 19 being in contact therewith constitute a lightly doped drain (LDD) type source/drain region of the PMOS transistor in the logic circuit region (b).
FIG. 3 is a sectional view illustrating a step of forming first through third titanium (Ti) silicide films 21a, 21b and 21c using a salicide process. In more detail, the gate oxide layer 9 is entirely blanket-oxide-etched to expose first through third high-concentration source/drain regions 17a, 17b and 19. In this case, since the thickness of the gate oxide film 9 is much thinner than that of the spacers 16, the height and width of the spacer 16 change little during the etching step. The natural oxide film on the first through third gate patterns 11a, 11b and 11c is also removed to expose the top surface of the first through third gate patterns 11a, 11b and 11c. Subsequently, a Ti film is formed to a thickness of about 200 .ANG. over the resultant structure and is annealed under a nitrogen atmosphere. In such a manner, if the Ti film is annealed, a first Ti silicide film 21a is formed on the first gate pattern 11a and the first high-concentration source/drain regions 17a and at the same time a second Ti silicide film 21b is formed on the second gate pattern 11b and the second high-concentration source/drain regions 17b. Also, a third Ti silicide film 21c is selectively formed on the third gate pattern 11c and on the third high-concentration source/drain regions 19. In this case, the Ti film formed on the spacers 16 and isolation film 3 remains in an unreacted state. Next, the unreacted Ti film is removed to isolate the gate patterns 11a, 11b and 11c from the neighboring source/drain regions. The unreacted Ti film may be removed using a NH.sub.4 OH solution. Alternatively, if tantalum is used as a refractory metal, H.sub.2 SO.sub.4 may be used.
Next, although not shown, an interlayer insulating film is formed on the resultant structure and a bit line connected to the source region (or the drain region) of the cell transistor is formed. Then, a planarized insulating film is formed over the entire surface of the resultant structure where the bit line is formed, and a cell capacitor comprising a storage electrode connected to the drain region (or the source region) of the cell transistor, a dielectric film and a plate electrode, is formed, thereby completing a DRAM cell in the cell array region (a).
According to the aforementioned conventional method of fabricating transistors, crystalline defects occur in the first and second high-concentration source/drain regions and these defects can increase junction leakage current. Therefore, charges stored in the storage electrode of the cell capacitor may be readily depleted through leakages and this may cause malfunction of the semiconductor device. To prevent malfunction, short cycle refresh times may be required to "recharge" the storage electrodes, however, such short cycle refresh times lead to increased power consumption.